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Toshiba starts sampling of 512-megabit XDR DRAM
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Posted on Thursday, December 25 2003 @ 21:59:39 CET by Thomas De Maesschalck |
Toshiba today announced that it has started to sample 512 megabit XDR DRAMs with a data transfer of 3.2GHz, based on Rambus his XDR memory interface technology. It offers Octal Data Rate, which transfers eight bits per clock cycle unlike todays DDR memory which only transfers two bits per clock cycle.
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Toshiba today made available samples of three versions of the new ultra high performance memory, TC59YM916AMG32A, TC59YM916AMG32B, TC59YM916AMG32C.
Next-generation broadband applications will process large volumes of data at higher speed in real time and will require large-volume, ultra high-speed memory chips. Toshiba meets these needs with its XDR DRAMs.
"Toshiba has been playing a leadership role in realizing XDR DRAM technology," said Shozo Saito, Technology Executive of Semiconductor Company at Toshiba Corporation. "In October 2002, we were first to license Rambus's most advanced technologies, and we have promoted their development ever since. Our efforts have borne fruit, as we are first in the world to sample XDR DRAM, and do so well ahead of our original schedule. The start of sample shipments of first generation XDR DRAM is a significant step to supply high-performance products for our customers. We aim for mass production in 2005, and to secure our leading position in this business area."
"We are pleased that Toshiba has delivered the first XDR DRAM samples ahead of schedule. Toshiba has taken the first step in providing the market with high-quality, cost-effective XDR DRAMs for the next-generation of innovative broadband products," said Laura Stark, vice president of the Memory Interface Division at Rambus. “We've shared a long and mutually beneficial relationship with Toshiba and look forward to continuing our work with them in making XDR DRAM a success in the marketplace."
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| Model
Numbers |
TC59YM916AMG32A; TC59YM916AMG32B;
TC59YM916AMG32C |
| Configuration |
4 megabits word x 8 banks x 16 bits |
| Max.
Data Rate |
3.2 Gbps |
| Cycle
Time |
40 nanoseconds; 50 nanoseconds; 60
nanoseconds |
| Power
Supply |
1.8V VDD |
| Interface |
DRSL (Differential Rambus Signaling Level) |
| Latency |
27 nanoseconds; 35 nanoseconds; 35
nanoseconds |
| Package
Size |
1.27 x 0.8mm pitch BGA |
More info about XDR DRAM can be found here
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