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IBM makes watercooled 3D chips

Posted on Saturday, June 07 2008 @ 17:10:17 CEST by


IBM researchers have developed the first watercooled 3D chips stacks, the firm says this design promises to advance Moore's Law in the next decade and significantly reduce energy consumption of data centers.
These so-called 3-D chip stacks – which take chips and memory devices that traditionally sit side-by-side on a silicon wafer and stacks them together on top of one another -- presents one of the most promising approaches to enhancing chip performance beyond its predicted limits. This follows IBM’s leadership in advancing chip-stacking technology in a manufacturing environment a year ago, which shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips.

“As we package chips on top of each other to significantly speed a processor’s capability to process data, we have found that conventional coolers attached to the back of a chip don’t scale. In order to exploit the potential of high-performance 3-D chip stacking, we need interlayer cooling,” explains Thomas Brunschwiler, project leader at IBM’s Zurich Research Laboratory. “Until now, nobody has demonstrated viable solutions to this problem.”

3-D chip stacks would have an aggregated heat dissipation of close to 1 kilowatt—10 times greater than the heat generated by a hotplate—with an area of 4 square centimeters and a thickness of about 1 millimeter. Moreover, each layer poses an additional barrier to heat removal.

Brunschwiler and his team piped water into cooling structures as thin as a human hair (50 microns) between the individual chip layers in order to remove heat efficiently at the source. Using the superior thermophysical qualities of water, scientists were able to demonstrate a cooling performance of up to 180 W/cm2 per layer for a stack with a typical footprint of 4 cm2.

“This truly constitutes a breakthrough. With classic backside cooling, the stacking of two or more high-power density logic layers would be impossible,” said Bruno Michel, manager of the chip cooling research efforts at the IBM Zurich Lab.
More info at IBM.




 



 

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