Qimonda started volume production of Rambus XDR DRAM memory chips for the PlayStation 3:
Qimonda started to ship first samples of the 512Mb XDR DRAM in January 2008. The XDR memory solution extends the Qimonda specialty RAM portfolio to better serve high-performance and high-bandwidth applications for the fast growing global computing and consumer electronics markets.
“We are very proud to have started the volume production of our XDR product for PS3. This is a further milestone reflecting our product diversification strategy and demonstrating our leading position in the specialty memory market,” said Robert Feurle, Vice President Business Unit Specialty DRAM of Qimonda AG. “We are prepared to support all our customers with XDR DRAM in various applications.”
The XDR memory architecture is proven in high-volume, cost-competitive applications. Qimonda’s XDR DRAM, operating at 3.2Gbps, provides 6.4GB/s of peak memory bandwidth with a single, 2-byte wide device. With a roadmap extending to 6.4Gbps, providing 12.8GB/s of bandwidth per device, XDR DRAM provides an order of magnitude higher performance than today's standard memories. With XDR DRAM, designers can achieve unprecedented performance with the fewest devices.
"Qimonda’s leadership and commitment to the XDR memory architecture expands the supply for this advanced memory solution for consumer and computing applications," said Sharon Holt, senior vice president of worldwide sales, licensing and marketing at Rambus. "We look forward to continuing our partnership with Qimonda on future XDR memory solutions for high-volume applications demanding breakthrough performance.”
Backed by comprehensive engineering support services that range from chip design to system integration, the award-winning XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase™ circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.