The reason why AMD decided to scrap DDR-II 667 was because it had predicted, or perhaps just hoped, that by the time of migration to the new socket, the latencies of DDR-II would fall to the DDR-I level, and the ideal pick would be 2.5 and 3 latencies at the worst. Sadly for AMD, things went in the other direction and the only logical conclusion was to implement support for higher memory speeds. As memory standards develop, there is a possibility that AMD will add support for faster DDR-II memory by just updating the microcode, but things are far more complicated than that.More details over at The Inquirer.
The answer is simple in theory. Add another level of cache, go for a big one and you’re home free. In fact, by creating a larger L3 cache, AMD will have the opportunity to reduce the size of L2 cache and save die space. 64+64 L1, 512KB or 1MB L2 and 2-4MB of L3 are the first things that comes to mind. The cache would of course, keep all two or four cores happy and keep the data flowing.
AMD and their DDR2 issues
Posted on Saturday, March 25 2006 @ 10:50 CET by Thomas De Maesschalck