Posted on Monday, May 08 2006 @ 2:22 CEST by Thomas De Maesschalck
Intel's slides for an upcoming conference in Asia show the Itanium 'Tukwila' will be a quad-core processor with an on-die FB-DIMM memory controller.
The FB-DIMM controller likely supports 4 channels of memory, possibly more. As a result of the lower memory latency, Tukwila requires less cache than its predecessor. Montecito featured 27MB of cache, for two processors, while Tukwila is reported to have 6MB of L3 cache per core, or 24MB for each MPU. Preliminary diagrams also indicate that there is on-die switch for traffic between the four cores and caches on each chip.
Another of the main new features if the Common Systems Interconnect (CSI) which is a low latency, point to point, serial interconnect that uses differential signaling. Read on over at
RealWorldTech. Intel estimated Tukwila will deliver 40GFLOPS.
