Sun Niagara II details unveiled

Posted on Friday, Aug 25 2006 @ 02:52 CEST by Thomas De Maesschalck
DailyTech has some info about Sun's Niagara II:
The presentation was presented today at the Hot Chips 18 conference at around 4:30pm PST. Sun’s new Niagara II chip is the second multi-core offering set to join the current multi-car UltraSPARC T1. Confirmed specifications of Niagara II include the ability to execute up to 64 simultaneous threads and one floating-point unit per core.

Niagara II processors will ship with eight cores that all share a single 4MB pool of L2 cache. It will also have a very short eight-stage pipeline and 12-stage FPU pipeline. FBDIMM memory is supported with four dual channel memory controllers for an insane amount of memory bandwidth. PCI Express will also be supported with Niagara II processors too.
More info over here.


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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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