AMD says CPU core control key to power efficiency

Posted on Monday, Sep 04 2006 @ 17:14 CEST by Thomas De Maesschalck
AMD says they are focusing on clock speed control of the individual cores of quad-core processors to allow the processors to stay in the same power envelope as their dual-core predecessors.
Intel has been touting its quad-core processors "Kentsfield," likely to be named Core 2 Quadro, and "Clovertown," a future member of the Xeon DP 5000 series, since the beginning of this year and recently announced that it will be releasing Kentsfield as high-end desktop CPU in time for the Christmas season.

AMD will counter Kentsfield and Clovertown with a desktop and a new Opteron chip, but details are scarce. What we learned earlier is that the first quad-core, likely the Opteron variant, will launch in mid-2007 and that it will be a 65 nm chip, with a 45 nm version likely to follow in the first half of 2008. During a recent presentation, AMD provided a few more pieces of information on the architecture of the processor and how it will be able to reach a 68 watt power envelope.

While clock speeds have not been revealed, each of the four cores will integrate 64 KB L1 Cache and 512 KB L2 cache. The native quad-core architecture will also include a 2 MB shared L3 cache, which may increase in capacity over time. The processor will have a total of four Hypertransport links - up from three today - that provide a total bandwidth to outside devices of 5.2 GB/s. AMD is also thinking about integrating support for FB-DIMMs "when appropriate."
Read on over at TG Daily.


About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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