Intel to present SSE4 this week

Posted on Tuesday, Sep 26 2006 @ 16:28 CEST by Thomas De Maesschalck
Intel's Fall Developer Forum started today and that means you'll get a huge amount of Intel news the coming days!

One of the major announcements is expected to be SSE4, according to The Inq.

This new instruction set is called Gesher New Instructions (GNI) and unlike SSE3, Intel will heavily promote them. It's said that these instructions will be quite useful.


About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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Re: Intel to present SSE4 this week
by Anonymous on Tuesday, Sep 26 2006 @ 20:50 CEST
SSE4
Indicated by CPUID.01H:ECX.SSE4 [Bit 9] = 1 (from cpu-z hacked).

Three-byte Opcodes (like AMD's 3DNow!) from Intel's official documents:
pshufb, packed shuffle bytes: (66) 0f 38 00
phaddw, packed horizontal add words: (66) 0f 38 01
phaddd, packed horizontal add double words: (66) 0f 38 02
phaddsw, packed horizontal add signed words: (66) 0f 38 03
pmaddusbw, packed multiply unsigned bytes and add words: (66) 0f 38 04
phsubw, packed horizontal substract words: (66) 0f 38 05
phsubd, packed horizontal substract double words: (66) 0f 38 06
phsubsw, packed horizontal substract signed words: (66) 0f 38 07
psignb, packed toggle sign bytes: (66) 0f 38 08
psignw, packed toggle sign words: (66) 0f 38 09
psignd, packed toggle sign double words: (66) 0f 38 0a
pmulhrsw, packed multiply high rounded signed words: (66) 0f 38 0b
pabsb, packed absolute bytes: (66) 0f 38 1c
pabsw, packed absolute words: (66) 0f 38 1d
pabsd, packed absolute double words: (66) 0f 38 1e
palignr, packed align right: (66) 0f 3a 0f

Comments:
psignX & pabsX might prove useful in complex arithmetics; pmulhrsw is actually identical to 3DNow!'s pmulhrw (finally Intel's SSE has had all what 3DNow! can do, by adding packed single float arithmetics, pavgb and prefetch to SSE, horizontal arithmetics to SSE3, and pmulhrsw to SSE4); don't know what palignr exactly means.




Re: Intel to present SSE4 this week
by Anonymous on Tuesday, Sep 26 2006 @ 20:52 CEST
BTW, these numbers i got from
http://setiathome.berkeley.edu/forum_thread.php?id=32096 and are from june 2006.

Interesting to find out what have changed..