Posted on Wednesday, October 04 2006 @ 1:58 CEST by Thomas De Maesschalck
The Register
reports AMD is planning to implement an intermediate interconnect called Socket AM2+.
AMD looks set to implement a Socket AM2 revision spanning the processor interconnect's current specification and the upcoming Socket AM3 due in 2008. That at least is what reports coming out of Taiwan citing local motherboard-maker sources claim.
According to a Chinese-language HKEPC report, the intermediate interconnect is currently called Socket AM2+. Like AM2, it will support both today's dual-core K8 CPUs plus next year's quad-core K8L chips. The bus speed will rise to 4GHz from today's 2GHz, thanks to the implementation of HyperTransport 3.0.
At this stage the interconnect is down as supporting DDR 2 memory - AM3's key feature is the ability to hook up to DDR 3, support for which is expected to be added to AMD's on-processor memory controller in the 2008 timeframe.
