Posted on Thursday, February 01 2007 @ 19:34 CET by Thomas De Maesschalck
Sources close to Intel
gave The Inq some information about a new Intel project called Stoutland. This project features a CPU with an integrated memory controller.
The plans, which are not PORs (plans of record) yet, include 4S glueless sockets using third party XNC and a fully connected CSI. This will provide 6.4GT/s or 4.8GT/s, an astonishing 72 second generation Boxboro PCIe lanes and four first gen PCIe lanes on an unused ESI port as well as six first generation ICH9 lanes. Legacy support will be added through ICH9.
The CPU integrated memory controller will include 4+1 FB-DIMM I and FB-DIMM2 channels, with the latter clocking 800/1066 and providing 32-64 DIMM support per system.
The Beckton CPUs provide four CSI per socket.
This technology may arrive by the second half of 2009. There's also the Thurley platform, this one arrives in the second half of 2008, which also features an integrated memory controller. It uses the Gainestown quad-core eight-threads processor.
