Shanghai is apparently more than just a cache-bump. AMD's documentation explicitly claims Shanghai will be the company's first 45nm processor. However, with a die shrink additional cache is one of the immediate architecture options as the smaller node allows for more transistors to fit on the chip die. Shanghai features 6MB of L3 cache.
Barcelona, the 65nm quad-core next-generation Opteron from AMD, is expected to launch this summer with 2MB of L3 cache. L3 cache on the K8L architecture is shared over all four cores, yet each core has an independent L2 cache as well. More details on how this new cache operation works was detailed in June 2006 on DailyTech.
All other features found on Barcelona will also make an appearance on Shanghai: AMD-Virtualization (previously codenamed Presido), RDDR2, and HyperTransport 3.0. Like Barcelona, Shanghai will also tentatively ship with dual and quad-core variants. In 2008 AMD will tennatively add Secure Initialization to all its AMD-V platforms, including Shanghai.
45nm AMD Opterons in 2008
Posted on Monday, Feb 05 2007 @ 20:38 CET by Thomas De Maesschalck