The Register has some more information on IBM his Power CPU Roadmap for the Power5 and Power5+ processors :
IBM has already struck fear in the hearts of its competitors with the dual-core Power4 chip and looks set to apply more pressure on rivals with the future processors.
The Power5 processor will first appear in 2004 at the heart of the Squadron family of servers. These systems will scale from 1 to 64 processors. IBM's current large SMP - the p690 - only makes it up to 32 Power4 chips.
The first Power5 chips will come in at 1.4GHz and make their way up to 2.0GHz before being replaced by the Power5+ chips. It's here that things start heating up with the Power5+ said to run between 2.0GHz and 3.0GHz.
With the Power5 family, IBM is looking to make a number of improvements. Of note, the company hopes to drive memory bandwidth to more than 800GB/s in an SMP, speed up buses and make it possible to run multiple partitions on a single CPU.
IBM plans to improve its floating point performance with the Power5 - a nice competitive boost against Itanium 2. In addition, IBM expects to see gains with its simultaneous multithreading (SMT) technology. IBM claims to be able to turn the SMT technology off and on as needed, depending on the software load.
With "run multiple partitions on a single CPU" they don't mean something like harddisk partitions, but the ability to run multiple "virtual pc's" on one CPU. They also have some information on the Power6 from IBM :
With Power6, IBM boasts about "very large frequency enhancements," which is not a good sign for competitors. The chip is due out in 2006 or 2007 and will be used in all non-Intel servers. Yep, the zSeries, iSeries and pSeries will all run on the same chip. The Power6 chip appears to be known as the ECLipz project. Some kind of Sun reference?
Source : The Register (some more detailed information is in that article also)