Why AMD introduces Socket 939

Posted on Sunday, August 10 2003 @ 6:29 CEST by Thomas De Maesschalck
The Inq has written a very nice story about the 940-pin Opteron and 939-pin Athlon FX situation. In September we will see the Athlon64 from AMD, it will come in two flavors ; a 754-pin normal version with single memory channel which will be the cheapest, and a 940-pin FX version which will have dual channel memory.

Now the 940-pin version is exactly the same as the Opteron 1xx CPUs from AMD which are used for servers, it uses the same motherboard and the same memory. The Opteron uses Registered ECC (Error Correction Code) memory with a max speed of DDR333. DDR400 memory is supported by the controller, but not possible because there is no official specification for it yet from JEDEC. So you are stuck with DDR333, and the slower timings that ECC memory brings.

The cheaper 754-pin version does works with normal DDR400, which is also cheaper and has faster timings than ECC memory. So this would give the 754 better results in some benchmarks, and like the Inq writes : "leading no doubt to a flurry of benchmarks showing how the more expensive version is 'kRaP d00d'." And this would not be good for AMD.

  The problem now is that AMD is faced with having its flagship consumer CPU saddled with slow, expensive, hard to find RAM, and it can't fix it without a major redesign. There are two memory controllers on the Opteron based chips, and one on the Athlon64 non-FX line. The controllers can act in concert, or separately, depending on a lot of things. It seems that AMD has chosen to implement them in concert on the current Opterons, so you must add DIMMs in pairs. This means you can have two or four DIMMS per chip. If you use DDR400, as everyone will on the Athon64s, and it can support three DIMMS, you are artificially capped at two DIMMS. Since both are necessary to start with, there is no expandability without throwing DIMMs away. Not good.

The way to solve this problem is to split up the memory controllers to act in two channels of 64 bits instead of one 128 bit channel. This would effectively halve the number of individual chips that need a clock signal sent to them, allowing for three or four DIMMs per channel, most likely three. Best of both worlds, so why doesn't AMD implement this at the Athlon64 launch in a month or so? Simple, it didn't connect the pins for the clock distribution of the second channel. To fix this, all it needs to do, is redo the Opteron package, make all new motherboards, and convince everyone not to use the old chip in the new boards, and vice-versa, easy enough.

But AMD is not doing that, because servers do not need this, they require the more expensive RAM for the Error Correction memory. But they have solved the problem for the high end customers market! How? Socket 939!

The Inq is very sure that the Socket 939 will an Opteron, with other pins connected to allow 2*64 bit memory utilization. They also write that most likely you will not be able to get a 940-pin CPU in a socket 939 motherboard, or a 939-pin CPU in a socket 940 motherboard.

Source : The Inquirer

About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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