THESE DAYS, we don't hear much about the Itanium - after all, do we need to? Intel is confident of a decent performance position in the current 1S, 2S market and across the 1S to 4S server space (some 95 per cent of the market, after all) once the Tigerton CPU with quad-FSB Caneland chipset comes out. The Core 2 family has pretty good integer and FP performance, the FSB still has a bit of speed potential (an official 1600MHz is not impossible, to my mind), and AMD isn't exactly experiencing perfect execution currently.
The CSI - common system interconnect (or call it coherent scalable interconnect, if you wish) - was originally associated with the Tukwilla Itanium generation. One that, in some now very old roadmaps, would have been out in the market right now. It would have been a nice example of good, year-1999 Alpha EV7 interface technology finally coming out on an Intel platform several years after the brutal Alphacide. But, oh well. EV7's simpler version, HyperTransport, has been doing exactly that already for the past three years anyway..
Intel Itanium and CSI analysis
Posted on Friday, Mar 02 2007 @ 01:25 CET by Thomas De Maesschalck