TSMC’s 45nm low power process (LP) provides twice the density of 65nm with significantly lower power and manufacturing cost per die. End products are expected to achieve 40 percent greater functionality or 40 percent smaller die size, with reduced power consumption. These factors are particularly crucial for system on chip (SoC) designs with an ever-smaller footprint for cell phones, portable media players, PDAs and other handheld devices.
TSMC’s 45nm general purpose and high performance process (GS) provides more than double the density and a greater than 30 percent speed enhancement over the previous generation at similar leakage power, which is especially critical to support applications in PC, networking, and wired communication. The performance boost of 45nm LP and GS has already earned broad acceptance and support among customers, EDA, and IP partners.
TSMC’s 45nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. With an exceptionally high gate density and high-density 6T SRAM cell, more than 500 million transistors will easily fit into a 70mm2 die area. TSMC’s Low Power (LP) 45nm process is expected to be available first, followed soon after by the General Purpose and High Performance (GS) process. In addition, the 45nm logic family includes a low-power triple gate oxide (LPG) option. All three processes offer multiple Vt core devices and 1.8V, 2.5V, 3.3V I/O options to meet different product requirements.