Now, positioned as an advanced acceleration platform and still targeting to enhance PCIe architecture and performance, the Geneseo project is aimed – among other goals – to propose a common programming model for special-purpose applications, such as math-intensive transactions (financial, scientific and economic models), embedded content processing (data mining, encryption, compression, XML) and visualization and media processing (graphics, video, speech), Intel said. The company estimates the 0.7 and 0.9 revisions of the Geneseo specification to be completed in the second half of 2007, while final dates will be determined by the PCI Special Interest Group (PCI-SIG).
The 1.0 revision should be finished in the first half of 2008, Intel said, adding that the industry will likely start the adoption of Geneseo in the second half. The company also noted that Geneseo will be compatible with existing PCI architecture and infrastructure, so there will be no collisions with current accelerators using PCIe technology. Booting processes for existing operating systems will also remain unchanged, Intel added.
Intel Geneseo roadmap
Posted on Wednesday, Apr 18 2007 @ 02:15 CEST by Thomas De Maesschalck