AMD K10 processor details unveiled

Posted on Thursday, May 10 2007 @ 14:50 CEST by Thomas De Maesschalck
FUD Zilla once again reports about some juicy details of AMD's upcoming K10 processors. They've just published a list with 20 key features of this processor family:
First of all, the K10 has an integrated DDR2 memory controller with memory prefatcher and the K10 core has 64kb of L1 instruction cache + 64 KB data cache. It also has on chip L2 and L3 cache and this varies depending on the core. The Barcelona / Agena quad core K10 for example has 4x512 KB L2 and 2 MB of L3 cache. K10 supports 32 Byte instruction fetch, instruction precode and branch prediction during cache line files, decoupled decode / execution code, 3-way AMD64 instruction decoding, sideband stack optimiser, dynamic scheduling and speculative execution.

The new core also features 3-way integer execution and address generation, 3-way 128 bit wide floating point executions, Enhanced 3Dnow! Architecture, MMX, SSE, SSE2, SSE3 & SSE4A Single instruction multiple data (SIMD) instruction extensions.

Further the CPU can cope with advanced bit manipulation instructions, super forwarding, prefetch into L1 data cache, deep out of order integer & floating point execution, 8 additional XMM registers (SSE, SSE2, SSE3 and SSE4A) & 8 additional GPRs in 64 Bit mode.

Last but not the least is Enhanced HyperTransport architecture. If this is too much for you don’t worry, it is too much for most of us, but we like that the K10 supports SSE4A so it might have a fighting chance in encoding.

About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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