A Power 6 can thrust data of 64B/two cycles to Data Level One cache, with an aggregate L2 bandwidth of 127B/5 cycles per core. Data from the SMP fabric onto the chip will achieve 67 per cent times 40B/two cycles at peak.More info at The Inq.
A dual core chip will have nine execution units per core, with 790 million transistors on a 341 square millimetre die, with seven way superscalar performance and two memory controllers per chip, while it will be built on SOI 65 nanometre CMOS.
Big Glue will offer a whole series of alternate Power 6 bins, swapping cache depending on what customers want to build into their systems.
IBM claims that its 65 nanometer technology will offer a 30 per cent performance improvement over 90 nanometre chips, and use a a high performance SRAM cell.
IBM Power6 CPUs to hit 4-5GHz soon
Posted on Monday, May 14 2007 @ 08:15 CEST by Thomas De Maesschalck