IBM officially introduced its new 4.7GHz dual-core Power6 server processor. According to IBM this new processor offers nearly double the speed of the Power5 generation at the same power consumption levels.
IBM’s new 2- to 16-core server also offers three times the performance per core of the HP Superdome machine, based on the key TPC-C benchmark (2). The processor speed of the POWER6 chip is nearly three times faster than the latest HP Itanium processor that runs HP’s server line. Even more impressive, the processor bandwidth of the POWER6 chip – 300 gigabytes per second -- could download the entire iTunes catalog in about 60 seconds – 30 times faster than HP’s Itanium.
But the new server offers more than just raw performance – it is the world’s most powerful midrange consolidation machine, containing special hardware and software that allows it to create many “virtual” servers on a single box.
Demonstrating its remarkable versatility, the new IBM System p 570, running the POWER6 processor, claims the No.1 spots in the four most widely used performance benchmarks for Unix servers – SPECint2006 (measuring integer-calculating throughput common in business applications), SPECfp2006 (measuring floating point-calculating throughput required for scientific applications), SPECjbb2005 (measuring Java performance in business operations per second) and TPC-C (measuring transaction processing capability) . This is the first time that a single system has owned all four categories. The new System p 570 now holds 25 benchmark records across a broad portfolio of business and technical applications.
The performance leadership is largely attributed the system’s balanced design. Unlike competing servers, IBM succeeded in scaling the new server’s processor performance and system design (cache sizes and bandwidth) in a balanced way. The POWER6 chip has a total cache size of 8MB per chip – four times the POWER5 chip – to keep pace with the awesome processor bandwidth. By contrast, many other servers concentrate mainly on processor performance, at the expense of the server’s ability to feed data to the chip at a rate that takes advantage of the processor’s speed.