ARS Technica takes a look at cache and memory designs in the many-core CPU era. Here's a short snip:
As Moore's Law increases, the amount of parallel hardware and the number of threads that can access a single, shared resource, this problem will continue to grow. Indeed, resource contention challenges have the potential to scale fairly well with increases in core and thread counts, so chip multiprocessor (CMP) designers have been working on ways to address this issue since the very start of the dual-core era.
In the present article, I'll take a look at the issue of resource contention and at one of Intel's proposed methods for overcoming this challenge: the quality-of-service-aware memory hierarchy.