AMD spilled the beans about the new SSE5 instruction set which it will first use in the Bulldozer core in 2009. The SSE5 instruction set features 46 base instructions that expand to 170 total instructions, enabling more performance and reduced processor load.
Precision control, rounding, and conversion instructions
Multi-core processor technology and the integration of specialized co-processors are effective methods for extending performance limits. Equally important is enabling the ability to maximize the efficiency of each core by reducing the total number of instructions needed to achieve the same result. SSE5 helps maximize the output of each instruction and consolidates code base by introducing functionality previously only found in specialized, high-performance architectures, to the x86 platform:
3-Operand Instructions A computing instruction is executed by applying a mathematical or logical function to operands, or inputs. By increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective instruction. The ability to execute 3-Operand Instructions is currently only possible on certain RISC architectures.
Fused Multiply Accumulate The 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The Fused Multiply Accumulate instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications.