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AMD K10 - support for 1600MHz DDR3, L3 cache in Northbridge

Posted on Monday, September 17 2007 @ 14:49:44 CEST by

Ten days ago AMD published a 365-page long whitepaper on its site called "BIOS and Kernel Developer's Guide for AMD Family 10h Processors". FUD Zilla sifted through this long and boring document and learned some interesting things about AMD's K10 processors.

One of the first things they discovered is that the K10's memory controller supports both DDR2 and DDR3 memory:
We know that Intel aren't too keen on "combo" boards with both DDR2 and DDR3 as the performance isn't great for either memory type, even though it offers an upgrade path for the user.

MSI removed the DDR2 memory slots from its X38 board due to this and the question is if AMD is doing this purely for backwards compatibility or not.

So far there are no AMD compatible motherboards that supports DDR3 and we don't expect to see any all that soon. It's also more complicated to design a motherboard for DDR3 due to the shorter trace length compared to DDR2.
The document also indicates the types of memory that are supported. This includes DDR2 1066MHz and 1066MHz, 1333MHz and 1600MHz DDR3 memory modules.
There does seem to be some limitations though, although we're not quite clear on the information as different parts of the documentation mentions different things, but you might only be able to run two DIMM's when you use DDR2-1066 or DDR3-1066. Why this is, we're not sure.

AMD has also added support for up to 8GB per DIMM, although as the documentation caters for both the Phenom and the Opteron processors, some of the information isn't clear in terms of which CPU it talks about. Some limitations might be imposed on the consumer level products, just as Intel has done in the past with its consumer level chipsets.
The last discovery is that the new AMD processors feature L3 cache in the northbridge:
This might seem odd at first, but it does sort of make sense when you consider that the L3 cache is shared between each of the two or three CPU cores.

Since each core already has L1 and L2 cache, 512kb in the latter case, there's no need for the L3 cache to be that close to the cores. It's still close enough as to not have a huge performance impact and it should make it easier to "recycle" CPU's with broken L3 cache as something else.



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