Yesterday at the 2003 IEEE International Electron Devices Meeting in Washington, DC, AMD showed additional information about its SOI (silicon-on-insulator) transistor design, while providing information about the succesful use of this technique in its current CPUs:
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Towards a Complete 45 Nanometer (nm)
Solution
AMD’s new transistor is expected to offer a high-confidence solution to many
of the most critical challenges the semiconductor industry expects to face at
the 45 nm technology generation (or “node”). A nanometer is a billionth of a
meter.
“Each time you shrink transistors in a new
technology generation, it presents additional challenges. Reducing electrical
leakage when the transistor is off is one challenge, but equally important is
maximizing electrical flow when the transistor is on,” said Ming-Ren Lin, AMD
Fellow. “While research from other companies often addresses these challenges
individually, AMD’s approach is to address all of them as an integrated
whole.”
Currently, the International Technology Roadmap
for Semiconductors forecasts that transistor gates, the primary parts of
transistors that turn the flow of electricity on and off, will need to be as
small as 20 nm in order to achieve performance projections for the 45 nm
generation. Today, minimum gate lengths in the highest-performance
microprocessors from AMD are approximately 50 nm.
“Aggressively shrinking the size of
transistor gates is fundamental to ever-increasing transistor performance, and
this trend shows no sign of abating,” added Lin. “To maintain this pace of
innovation, it is imperative that leading-edge manufacturers incorporate
innovative transistor structures such as AMD has done here.”
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Unique Multi-Gate Design
AMD’s new transistor design uses three gates, instead of one as in today’s
transistors, and incorporates several innovations that allow for continued
transistor gate scaling down to 20 nm and below, while providing increased speed
and decreased electrical leakage. Further, AMD’s transistor is not dependent
upon the use of so-called “high-k” gate dielectric materials, which have
been shown to have negative effects on some aspects of transistor performance.
“We have taken a structural approach that
utilizes conventional materials in new ways to provide a demonstrated solution
at the 20 nm gate dimension. This is the kind of innovation required to drive
technology advancement well into the next decade,” stated Lin.
AMD research technologies used in the new
multi-gate design include:
- Fully depleted SOI (FDSOI): The next
generation of silicon-on-insulator (SOI) technology that increases the
performance and power-saving benefits of today’s SOI.
- Metal gates: Gates made from
nickel-silicide, rather than polysilicon as they are today, in order to
improve electrical flow while reducing unwanted leakage.
- Locally strained channel: A
revolutionary way of combining advanced materials in a geometry that
naturally “strains” the atoms within the transistor’s electrical path
so electricity can flow more fully.
AMD’s approach has resulted in transistors
that demonstrate record-setting performance with dramatically reduced current
leakage. For further technical details on AMD’s multi-gate research presented
at the conference, visit www.amd.com/IEDM03_triple.
Extending the Benefits of SOI
AMD’s next-generation SOI research builds upon the company’s current
successes using SOI in a high-volume manufacturing environment within AMD Fab
30. AMD detailed these successes at IEDM as well, giving in-depth information on
the SOI technologies used in AMD64 processors to increase product performance
while reducing power requirements.
“SOI is a key contributor to the AMD Opteron™
processor delivering leading-edge 32-bit and 64-bit performance, while
minimizing power consumption,” stated Sander. “Lower power means less heat.
For enterprise IT staffs, less heat can be a major factor in reducing total cost
of ownership and helping to ensure reliability.”
AMD also provided information for the first
time on its leadership in introducing what are known as “low-k” dielectric
materials for improved circuit performance. These low-k materials are used to
insulate the copper interconnect lines that conduct electrical signals across
the chip and reduce the energy that is needed to propagate these signals. AMD
was a leader in the introduction of low-k materials into a high-volume
manufacturing environment, starting with its 130 nm process in AMD Fab 30.
