Posted on Wednesday, October 31 2007 @ 12:34 CET by Thomas De Maesschalck
The Itanium platform’s mission-critical support is strengthened by a new feature called Core Level Lock-Step that improves the data integrity and reliability of applications by eliminating undetected errors in the core. Core Level Lock-Step joins existing Socket Level Lock-Step technology to deliver greater reliability, availability and serviceability (RAS) by guaranteeing that calculation results are consistent among the cores and sockets.
Another new feature, Demand Based Switching (DBS), reduces server power consumption during low utilization periods, which can result in energy cost savings.
The 9100 series features clock speed of up to 1.66 GHz and 667 MHz Front Side Bus (FSB) within a 104W power envelope. A three-load bus – two processors and a chipset on the same bus - provides increased bandwidth for enterprise and high-performance computing tasks.
Six Intel dual-core and a single-core Itanium 9100 series processors are shipping today, with lock step parts to begin shipping in the first quarter of 2008. Prices range from $650 to $3,450 depending on order volume, features and performance.
