The Tech Report has published more details about the erratum in the L3 cache of AMD's Opteron and Phenom 9500/9600 processors. The site says AMD stopped shipments of quad-core Opteron CPUs but is still shipping Phenom processors to large PC builders and distributors.
The site claims AMD knew about the problem before the launch of the Phenom and misled the public that the problem only occurred at clockspeeds of 2.4GHz or higher. The chipmaker is working on a BIOS patch with a CPU microcode update but unfortunately this patch will lower the performance of the processors by as much as 10%. Some sources even claim the performance penalty may even be as high as 10-20% in some applications.
In order to better understand this problem, TR spoke with Michael Saucier, Desktop Product Marketing Manager at AMD. Saucier confirmed that the TLB erratum's effects are felt when the chip is experiencing high utilization. AMD has stated previously that virtualization workloads can lead to this problem, but Saucier clarified that other workloads can trigger system hangs, as well. He characterized the issue as a race condition in the TLB logic "where the other guy wins who isn't supposed to win," and said the likelihood of the erratum causing a system hang is extremely rare.
Apparently contradicting prior AMD statements on the matter, Saucier flatly denied any relationship between the TLB erratum and chip clock frequencies. He also said there's no relationship between clock speeds and the performance degradation caused by the BIOS-based fix for the erratum. AMD had previously cited the TLB erratum as the primary motivation behind its decision to delay the 2.4GHz Phenom variant.
Consumers who don't want to buy a faulty chip will have to wait for the B3 revision of the 9500 and 9600 processors but it's not clear when these chips will arrive. AMD estimates the B3 revision, including the 2.4GHz Phenom 9700 and 2.6GHz 9900, will arrive in mid to late Q1 2008.
The Tech Report speculates this may be the reason why AMD only let reviewers test the Phenom processors in a controlled environment:
Incidentally, the presence of the TLB erratum may explain the odd behavior of AMD's PR team during the lead-up to the Phenom launch, as I described in my recent blog post. The decision to use 2.6GHz parts and to require the press to test in a controlled environment makes more sense in this context. Since 2.6GHz Phenoms, when they arrive, should be based on the B3 revision of the chip with the TLB erratum fix, AMD could justifiably argue that their performance won't be limited by the BIOS-based workaround. Saucier confirmed to us that the test systems at the Tahoe press event did not have the workaround enabled.
But the bad news doesn't stop here. The Tech Report received a retail sample of the Phenom 9500 processor and found out the chip uses a 1.8GHz north bridge clock instead of a 2GHz northbridge clock like the chips used in most reviews of the Phenom processor last month:
We don't yet have a BIOS with the workaround to test, but we've already discovered that our Phenom review overstates the performance of the 2.3GHz Phenom. We tested at a 2.3GHz core clock with a 2.0GHz north bridge clock, because AMD told us those speeds were representative of the Phenom 9600. Our production samples of the Phenom 9500 and 9600, however, have north bridge clocks of 1.8GHz. Because the L3 cache runs at the speed of the north bridge, this clock plays a noteworthy role in overall Phenom performance. We've already confirmed lower scores in some benchmarks.
Given everything we've learned in the past few days, our review clearly overstates Phenom 9600 performance, as do (more likely than not) other reviews of the product. We can't know entirely by how much, though, until we can test a Phenom system with the TLB erratum workaround applied.