The information says Silverthorne will have a two-issue, in-order pipeline with integer and floating point execution units, 32KB of iL1 cache, 24KB of dL1 cache, 512KB of L2 cache, and a 533MT/s front-side bus.
According to Ars, that suggests the chip harbors a design similar to that of the original Pentium processor, which was also a two-issue, in-order chip. Based on this find, the site extrapolates that Silverthorne will be at a performance and power efficiency disadvantage compared to RISC embedded processors from the likes of ARM: "I think we can safely assume at this point that Silverthorne will be clock-for-clock slower and less efficient than a comparable ARM part, especially on integer-intensive Web and productivity apps." Instead, Intel will have to rely on its process technology advantage to stay competitive, with 45nm Silverthornes set to fight it out against 65nm ARM chips.
Intel Silverthorne mobile CPU slower than expected?
Posted on Friday, Dec 14 2007 @ 01:00 CET by Thomas De Maesschalck