AMD Phenom B3 has no TLB errata

Posted on Saturday, Jan 12 2008 @ 03:10 CET by Thomas De Maesschalck
The Inq had a chat with Pat Moorehead from AMD and can confirm that the upcoming Phenom B3 chips won't have any TLB bugs:
When the rumours started to fly, I called AMD and talked to Pat Moorehead who answered all of my questions. The B3s are not bugged, period. The fix was tested on B2 silicon and verified (Don't ask, the elves who work at the Fraternal Order of Silicon Repair Mythical Creatures Local 17 get antsy if you reveal their secrets).

Basically there is no B4, there won't be a B4, and the next stepping is Cx. The Cx parts are the 45nm Shanghai cores, so the B3 will be the end of the line for 65nm. B3s are going to be sampling in the not so distant future, production in the end of Q1, and retail availability in Q2. That part is a slip.

In summary, B3 is fine. It is a little later than people expect, but what can you do? The fixed chips are on the way, sit tight, it is only a few weeks before this soap opera ends.


About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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