"My design borrows extensively from today's modern multicore CPUs," said Joseph Ashwood, an independent security cryptanalyst and design consultant residing in Gilroy, Calif. Ashwood was lead cryptanalyst for Arcot Systems in Santa Clara, Calif., before going independent in 2001. "As far as concurrency goes, my memory architecture shares some features with Fibre Channel."Source: EE Times
According to Ashwood, his architecture provides parallel access to bit cells on memory chips, breaking the serial bottleneck that is strangling nonvolatile storage media like flash, with an architecture that can be applied to any memory chip bit cell. The Ashwood memory architecture works by integrating smart controller circuitry next to the memory array on a single chip, providing parallel access to the array for hundreds of concurrent processes, thereby increasing throughput and lowering average access time.
"We have a new way of assembling the memory, with a few new elements I was led to by my experience with cryptography. I am basically applying very deep cryptographic techniques to memory architecture, resulting in a unique new design that is very fast and compact. Bringing in these new elements enables a lot of good things, especially concurrency, permitting hundreds of simultaneous memory operations," said Ashwood.
"Compared to DDR, for instance, my architecture goes inside the chip and reorganizes how the bit cells are accessed, thereby utilizing them much more efficiently," he added. "Transfer rate is faster, too—for instance, right now, DDR-II for DRAM only goes up to 12 Gbytes per second, but our architecture can deliver 16 Gbytes per second when using flash memory and is compatible with PRAM or any other nonvolatile semiconductor memory cells."
Memory to go multicore
Posted on Thursday, Jan 17 2008 @ 04:40 CET by Thomas De Maesschalck
Intel's and AMD's processor lineup is almost fully multi-core and it's possible that memory will follow the same approach: