Taiwanese foundy TSMC announced its 40nm process technology is ready and it will manufacture its first wafers with 40nm chips in the second quarter of 2008.
Following successful tapeouts and customer announcements of its 45nm process technology in 2007, TSMC has moved forward quickly and developed an enhanced 40LP and 40G process that delivers industry-leading performance with 40nm density. The 45nm node provided double the gate density of 65nm, while the new 40nm node features manufacturing innovations that enable its LP and G processes to deliver a 2.35 raw gate density improvement of the 65nm offering. The transition from 45nm to 40nm low power technology reduces power scaling up to 15 percent.
“Our design flow can take designs started at 45nm and target it toward the advantages of 40nm,” said John Wei, senior director of Advanced Technology Marketing at TSMC. “A lot of TSMC development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives,” he said.
TSMC has developed the 40LP for leakage-sensitive applications such as wireless and portable devices and its 40G variant targeting performance applications including CPU, GPU (Graphic Processing Unit), game console, networking and FPGA designs and other high-performance consumer devices. The 40nm footprint is linearly shrunk and the SRAM performance is fully maintained when compared to its 45nm counterpart, its SRAM cell size is now the smallest in the industry at 0.242µm2.
A full range of mixed signal and RF options accompany the 40G and 40LP processes along with Embedded DRAM, to match the breath of applications that can take advantage of the new node’s unbeatable size and performance combination.
The 40nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. The logic family includes a low-power triple gate oxide (LPG) option to support high performance wireless and portable applications. Both the G and the LP processes offer multiple Vt core devices and 1.8V, 2.5V I/O options to meet different product requirements.
TSMC’s CyberShuttle prototyping service can be booked for 40nm designs in April, June, August, October and December this year and first wave 45/40nm customers have already used above 200 blocks on completed multi-project wafer runs. The 40G and LP processes will initially run in TSMC’s 12" wafer Fab 12 and will be transferred to Fab 14 as demand ramps.
A 2.35 times raw gate density improvement over 65nm
Active power down-scaling of up to 15% over 45nm
Smallest SRAM cell size and macro size in the industry
General Purpose and Low Power versions for broad product applications
Dozens of customers in the design pipeline today
Frequent and regular CyberShuttle, MPW prototyping running