TSMC outlines 32nm process

Posted on Thursday, April 24 2008 @ 4:03 CEST by Thomas De Maesschalck
TSMC outlined details about its 32nm process, including the introduction of a high-k and metal-gate offering:
Last week, IBM Corp. and its technology alliance took the lead in the heated public relations battle by announcing the availability of a high-k and metal-gate offering for foundry customers at the 32-nm node.

Silicon foundry giant TSMC has been quiet about its efforts in the arena--at least until now. ''We will have high-k and metal-gate at 32-nm,'' said Rick Tsai, president and chief executive of the company, during a keynote at its 2008 Technology Symposium here.

Jack Sun, vice president of research and development, indicated that TSMC will provide various enabling options at the 32-nm node. For its 32-nm low-power process, the company plans to develop a third-generation triple-gate oxide technology.
Source: EE Times


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Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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