FUD Zilla heard AMD's Shanghai processor will have some IPC enhancements:
We can remind you that Dirk Meyer, the second in charge at AMD, has said that volume production of 45nm quad cores, including Shanghai, will start in Q4 2008.
The new Shanghai design will feature coherent HyperTransport 3.0 for processor to processor communication. The new 45nm Quad core will also increase the amount of shared L3 cache from 2MB with current Barcelona design to 6MB with Shanghai and this new Chinese chip promises instruction per clock (IPC) enhancements.
We were a bit shocked to see that currently there are no any plans for eight core Montreal 45nm chip but again this might be a desktop only chip, or AMD wants to keep this as a little surprise.