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Elpida discusses shrunken 65nm process, claims it competes with 50nm

Posted on Saturday, October 11 2008 @ 18:13:12 CEST by

DigiTimes had an interview with Elpida vice president for investment and public relations, Kumi Higuchi, about the company's new shrunken 65nm process for DRAM memory chips. Elpida claims the new process enables them to compete effectively with 50nm class processes currently being developed by rivals:
Q: While your company has come out with a shrunken 65nm process, Samsung Electronics and Hynix Semiconductor are migrating to 50nm-class nodes. How does Elpida see its current competition in terms of process advancement?

A: Our 65nm shrunken process is able to deliver 20% more chips than a typical 65nm-node 12-inch wafer with just a simple upgrade to our existing equipment, and minimal additional capital expenditure.

In comparison, Samsung's 50nm process will be able to ramp up chip output over 25% per 12-inch wafer, whereas Hynix's 50nm process will deliver 21% more chips. However, migration to the 50nm process also requires addition investment in production equipment which could push up overall equipment costs by 20%. We believe this will make the 50nm-class processes less competitive compared to our shrunken 65nm process.

Q: Does that then imply Elpida is going to slow down its development and investment in the 50nm node?

A: Prospects for the DRAM industry are still uncertain and so we have decided to use our cash on hand cautiously. The shrunken 65nm process will become our main process node. We will not commit more investment in the 50nm process until there is an upturn in the market or when the market for DDR3 begins to gain momentum.
Read more over here.



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