Posted on Thursday, October 30 2008 @ 0:00 CET by Thomas De Maesschalck
EE Times reports Intel will take the wraps off its new 32nm process for processors at the 2008 IEEE International Electron Devices Meeting (IEDM) in December.
According to the IEDM paper, Intel built a functional 32-nm, 291-Mbit SRAM array test chip with a 0.171-micron² cell size. The device has nearly 2 billion transistors, and an array density of 4.2-Mbit².
The test chip operated at 3.8-GHz at 1.1 Volt, according to the paper. Intel (Santa Clara, Calif.) is expected to deploy its first immersion lithography scanners at 32-nm. The 193-nm machines will be sourced from Nikon Corp. (Tokyo).
The process also makes use of a second-generation, high-k/metal gate technology, a strained channel, and nine levels of low-k interconnect dielectrics, according to a sneak preview of the paper.
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