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Intel Core i7 TLB bug reports are nothing to worry about (UPDATED)

Posted on Monday, December 01 2008 @ 20:35:05 CET by

FUD Zilla published a report today that there's a Translation Lookaside Buffer (TLB) bug in Intel's new Core i7 processor series. Most of you will still remember a TLB bug in AMD's Phenom processor resulted in a big blow for AMD as the "fix" resulted in a big performance drop but fortunately for Intel the Core i7 errata isn't as bad as some of the more sensational reports want you to believe.

Every processor has dozens of errata (bugs), but usually these don't result in problems in real-world situations. FUD Zilla refers to page 37 in a PDF about the Core i7 processor which lists a clarification of a problem with the translation lookaside buffers (TLBs) that may result in unpredictable system behavior in rare instances:
Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly.

Intel will update the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide in the coming months. Until that time, an application note, TLBs, Paging-Structure Caches, and Their Invalidation (http:// www.intel.com/products/processor/manuals/index.htm), is available which provides more information on the paging structure caches and TLB invalidation.

In rare instances, improper TLB invalidation may result in unpredictable system behavior, such as system hangs or incorrect data. Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms. For the processors affected, Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue.
The chip giant says they've provided a recommended update to system and BIOS vendors to resolve the issue, and the whole issue was solved long before any Core i7 processors hit the retail channel.

Furthermore, a quick search on Google will show you this errata was not only in the Core i7 processor but in various other Intel chips, including Core 2, Atom, Celeron, Pentium Dual-Core and Xeon series processors. The TLB issue has been known since 2007 and has been fixed via BIOS microcode updates, IMO this is nothing more than crying wolf and there's nothing to worry about.

UPDATE - December 2, 2008 @ 00:11: The Tech Report has received an official statement from Intel. Intel PR manager Dan Snyder explains the TLB clarification is a spec clarification, and a pointer to a previous document written in April 2007. This TLB issue was present in the Conroe architecture but has been fixed with a BIOS microcode update. The Core i7 (Nehalem) was never really affected by the bug.
The "AAJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS" document is a SPEC CLARIFICATION, and is simply a pointer to a previous document written in April 2007.

SPEC CLARIFICATION AAJ1 was initially added due to an issue on the Intel® Core 2 Duo processor which was previously corrected with a BIOS update; this issue does not impact the Nehalem Family of CPUs. There are errata on the Intel® Core i7 processor that relate to the TLB. These all relate to improper translations or error reporting, and all of those that impact functionality have been fixed via BIOS updates prior to Core i7 launch.



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