EE Times reports Rambus unveiled a set of new and existing interconnect technologies designed to meet the needs of memory in 2011 and beyond. The company hopes the industry will adopt the technologies as part of the pending DDR4 memory standard.
The concepts are promising, but a history of intellectual property disputes clouds the road to adopting them. Rambus is in litigation with three of the four top DRAM makers, one of the cases stretching into its ninth year.
Some of the IP issues originated in work on memory interconnects in the JEDEC group that defines next-generation DRAM standards, a group in which Rambus no longer participates. JEDEC executives--and a handful of the group's members—declined to comment on the status or outlook for DDR4.
As part of its announcement, Rambus outlined a handful of market requirements it believes will be key for main systems memory interconnects in 2011 and beyond. They include doubling today's DDR3 per-pin data rates to 3,200 Mbits/second, slashing active and idle power rates significantly and maintaining support for multiple dual in-line memory modules (DIMMs) per memory channel.
The company disclosed two new technologies as part of a new main memory initiative to address those requirements, module threading and a new single-ended version of its near-ground signaling technology.