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NVIDIA calls for tools to optimize power consumption

Posted on Friday, July 31 2009 @ 02:15:18 CEST by

In a keynote at the Design Automation Conference, NVIDIA Chief Scientist and Senior Vice President of Research William J. Dally said chip designers will need tool and techniques to optimize power, interconnect and locality. More info at EE Times.
Chip designers will need tool and techniques to optimize power, interconnect and locality, Dally said.

"We are really looking to EDA to give us power tools," Dally said.

Tools are needed to enable power exploration and analysis at the architectural levels, Dally said. "I want high-level tools that allow you to gain insights into power architectures very early in design," he said.

To succeed, the industry needs CAD tools that capture high-level design and intent, as well as new architectures and compilation to expose locality, Dally said.



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