Posted on Friday, July 31 2009 @ 21:28 CEST by Thomas De Maesschalck
AMD and HP researchers have proposed two extensions to the PCI Express 3.0 which aim to enable lower cost chips that could support multiple protocols and reduce processor overhead. The companies hope to get the extensions accepted as part of the draft PCIe 3.0 spec slated for early 2010.
The two extensions are independent of each other and have applications in graphics, high-speed I/O and embedded systems. Both require some changes to silicon and software.
A so-called protocol multiplexing extension would let chips dynamically switch between as many as seven different protocols in addition to PCIe using a shared set of chip pins, buffers and board traces. Resulting chips could use fewer pins, and OEMs would need fewer devices and could make more flexible systems.
Using the technique, for example, chip makers could design a single part that connects processors and accelerators via PCIe, Intel's Quick Path Interconnect or the coherent HyperTransport bus.
"This will enable hybrid computing to take off because a graphics chip could act like a host processor, and you could much more easily offload jobs from a CPU to a GPU or accelerator," said Michael Krause, an I/O specialist at HP.
More info
at EE Times.
