Intel blogger Ken Kaplan reports Westmere will be presented at the IDF in San Francisco from September 22-24, 2009:
Where Nehalem was new chip architecture design, Westmere is the next design being used to build processors that feature two 32nm cores with 4MB of cache that sit next to a memory controller and integrated graphics built on a separate, neighboring 45nm chip, all in one package. Westmeres will be the basis of upcoming all new Core chips (Core i3, i5, and 7) over the next few months.
Westmere processors will share some of the same features that were built into Nehalem, including Hyper-Threading and Turbo Boost (descirbed above).
Some Westmeres will feature HyperThreading will allow each core to handle two threads — or process two jobs at once.