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AMD details Bulldozer architecture

Posted on Tuesday, August 24 2010 @ 22:17:43 CEST by


AMD also talked about its Bulldozer architecture at the Hot Chips conference. This is the company's next-gen 32nm desktop architecture, it supports up to eight cores and delivers much higher instructions per second (IPC) than AMD's previous architectures. Full details can be read at TechPowerUp.
AMD codenamed its latest design "Bulldozer", and it features an x86 core design that is radically different from anything we've seen from either processor giants. With this design, AMD thinks it can outdo both HyperThreading and Multi-Core approaches to parallelism, in one shot, as well as "bulldoze" through serial workloads with a broad 8 integer pipeline per core, (compared to 3 on K10, and 4 on Westmere). Two almost-individual blocks of integer processing units share a common floating point unit with two 128-bit FMACs.

AMD is also working on a multi-threading technology of its own to rival Intel's HyperThreading, that exploits Bulldozer's branched integer processing backed by shared floating point design, which AMD believes to be so efficient, that each SMT worker thread can be deemed a core in its own merit, and further be backed by competing threads per "core".



 



 

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