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Rambus achieves new memory signaling breakthroughs

Posted on Tuesday, February 01 2011 @ 14:43:08 CET by


Rambus announced new breakthroughs in memory signaling. The company says its new SoC-to-memory interface can hit differential memory signaling speeds of up to 20Gbps and single-ended memory signaling of up to 12.8Gbps.
Rambus Inc. (NASDAQ: RMBS), one of the world’s premier technology licensing companies, today announced it has advanced differential signaling for SoC-to-memory interfaces to a groundbreaking 20 gigabits per second (Gbps) and developed innovations which can extend single-ended memory signaling to an unparalleled 12.8Gbps. Rambus has also developed innovations which enable a seamless transition for memory architectures from single-ended to differential signaling as data rates rise to meet the performance requirements of future-generation graphics and gaming systems. Rambus will demonstrate its breakthroughs in memory signaling technology this week at DesignCon 2011.

The latest technology advancements of Rambus’ Terabyte Bandwidth Initiative enable unmatched power efficiency and compatibility to single-ended memory architectures, including GDDR5 and DDR3. With the addition of FlexMode™ interface technology, a multi-modal, SoC memory interface PHY, supporting both differential and single-ended signaling, can be implemented in a single SoC package design with no additional pins. Rambus has achieved a power efficiency of 6 milliwatts (mW) per Gbps when operating at 20Gbps in a 40nm-process silicon test vehicle. These innovations address critical system challenges to extending signaling rates by addressing power efficiency and compatibility needs.

“We have paved multiple paths for the industry by providing solutions that extend single-ended signaling beyond today’s limits and developing the means for a seamless transition to differential signaling,” said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus. “By advancing data rates in an extremely power-efficient way, and enabling compatibility to current industry-standard memories, we have removed the technical and business barriers for customers to achieve unprecedented capabilities in their products.”

Through the Terabyte Bandwidth Initiative, Rambus has developed key innovations using its renowned signaling and memory architecture expertise. These Rambus patented innovations include Fully Differential Memory Architecture (FDMA), FlexLink™ C/A and 32X data rate. The latest addition to these innovations, FlexMode interface technology, enables support of both differential and single-ended memory interfaces in a single SoC package design. FlexMode technology achieves this with no additional pins through programmable assignment of signaling I/Os to either data or command/address.

Launched in November 2007, the Terabyte Bandwidth Initiative reflects Rambus’ ongoing commitment to innovation in cutting-edge performance memory architectures. The initiative serves as the foundation for future memory architectures that offer increased performance, higher and scalable data bandwidth, area optimization, enhanced signal integrity, and multi-modal capability for gaming, graphics and multi-core computing applications.



 



 

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