Samsung announced its foundry operation is preparing to run test-chip shuttles for customers beginning in the second half of 2011. The Korean tech giant will offer 20nm technology, a full node shrink from 28nm.
"Our 20-nm technology will be a full node shrink from 28-nm, enabling the approximate 50 percent area scaling that the industry has come to expect with each technology generation," Hunter also said in a posting on the company's website.
The 20-nm process is based on a planar bulk CMOS process with "gate-last" high-K metal gate (HKMG) and will be manufacturable with 193-nm immersion optical lithography on a limited minimum pitch. The minimum pitch is not shrunk to the maximum to reduce the need for time-consuming, costly double-patterning. Hunter predicts a 30 percent improvement in performance over 28LP at the same standby current.
Hunter does not talk about high-performance versus low-power variants merely stating that the Samsung process is suitable for making chips for both types of application; including smartphones, tablets, other portable consumer electronics as well as IT communications infrastructure.