Posted on Saturday, March 05 2011 @ 6:21 CET by Thomas De Maesschalck
EE Times reports Intel's Paolo Gargini
talked about the prospect of a field effect transistor combined with quantum tunneling as a way to reduce power efficiency.
Paolo Gargini, Intel Fellow and chairman of the International Technology Roadmap for Semiconductors (ITRS) used a talk at the Industry Strategy Symposium Europe held here by the SEMI industry organization, to discuss the prospect of a field effect transistor combined with quantum tunneling as a means of reducing power consumption while maintaining adequate performance.
Raising mobility through the use of non-silicon materials in the transistor channel remains a favored theme with Gargini but he appeared to push back the prospect of deployment until about 2020.
Gargini, discussed compound semiconductor on silicon, as he has done before. But he also discussed the arrival of multi-gate HKMG III-V devices on silicon substrates arriving by 2020. However he also discussed the need to optimize for power consumption rather than performance.
