Bright Side of News reports NVIDIA CEO Jen-Hsun Huang showed off a mockup of the Project Denver CPU die during his introduction speech at the company's annual Financial Analyst Day. I say mockup because the photo is little more than a resized picture of the Fermi die with some conceptual drawings.
The largest block on the die belongs to L1 Data Cache, while there is also L1 Instruction cache. While it is too early to discuss the actual features of this CPU core, we're really intrigued by some of the statements about the Project Denver core - mostly ranging in the field of attaching four Project Denver cores on a high-bandwidth interface such as existing GPU memory controller.
In theory, Project Denver cores inside the Maxwell GPU die should enjoy access to 2+TB/s of internal bandwidth and potentially beyond currently possible 320GB/s of external memory bandwidth (using 512-bit interface and high-speed GDDR5 memory). If nVidia delivers this architecture as planned, we might see quite a change in the market - given that neither CPUs from AMD or Intel don't have as high system bandwidth as contemporary graphics cards.