Posted on Tuesday, July 19 2011 @ 22:41 CEST by Thomas De Maesschalck
VR Zone
reports Intel is mulling the creation of a two lane PCI Express solution:
Why? Well, simply because PCI Express x1 doesn't offer enough bandwidth for a lot of bandwidth hungry devices, but PCI Express x4 is too wide for many peripheral chips, especially considering Intel's chipset limitations.
Many devices PCI Express peripheral chipsets such as SATA controllers and USB 3.0 host controllers really requires more than one lane of PCI Express bandwidth, as each lane in a PCI Express 2.0/2.1 system is "limited" to a theoretical maximum transfer speed of 5GT/s (Giga Transfers) or about 500MB/s, not taking into account overheads. PCI Express alleviates some of these problems by lowering the overhead and increasing the bandwidth per lane to 8GT/s or close to a real throughput of 1GB/s, but it's not that simple..
