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DDR4 to use 3D stacking?

Posted on Tuesday, December 20 2011 @ 22:12:21 CET by


X-bit Labs reports Micron's three-dimensional stacking (3DS) technology may be a core tech of DDR4 memory:
The idea behind 3DS is to use specially designed and manufactured master-and-slave DRAM die, with only the master die interfacing with the external memory controller. 3DS technology uses optimized DRAM die, single DLL per stack, reduced active logic, single shared external I/O, improved timing, and reduced load to the external world. This combination of features can improve timing, bus speeds, and signal integrity while lowering both power consumption and system overhead for next-generation modules, according to Micron.

In its video demo, Micron shows a timing limitation when reading from one rank and then from another. Due to the system limitation, there is a one-cycle gap on the data bus, which impacts overall system bandwidth. Micron’s 3DS devices offer the opportunity to eliminate this timing gap between read accesses from one rank to another. Our 3DS device can accept Read commands to different ranks so that the data bus is in constant use, claims Micron.




 



 

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