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Intel shares more Ivy Bridge details

Posted on Tuesday, February 21 2012 @ 13:11:52 CET by

EE Times reports Intel revealed more information about Ivy Bridge, you can read it over here. The chip packs up to 1.4 billion transistors in a package of 160mm² and is the first of Intel's client chips to support low-power 1.35V DDR3L and DDR power gating in standby mode.
Intel gave its first details public look into Ivy Bridge, the first processors to use its 22 nm tri-gate technology. Intel plans at least four major variants of the chip which packs 1.4 billion transistors into 160mm2 in its largest version.

Ivy Bridge packs 20 channels of PCI Express Gen 3 interconnect and a Displayport controller, Intel’s first chip to integrate PCIe. The move marks one small step into the long term quest of what an Intel executive called terascale-class clients.

The first Ivy Bridge chip targets a range of desktop, notebook, embedded and single-socket server systems with up to 8 Mbytes cache. Like previous Intel parts it integrates a memory controller and graphics, now upgraded to support DDR3L DRAMs and Microsoft DirectX 11.0 graphics APIs.



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