AMD's Piledriver core will be the first commercially available processor to implement the resonant clock mesh technology licensed from startup firm Cyclos Semiconductor. This technology promises a total IC power consumption reduction of up to 10 percent, by using on-chip inductors that interact with the capacitance of the clock signal distribution to "recycle" clock power instead of dissipating it on every clock cycle.
AMD claims it was able to seamlessly integrate Cyclos' technology into the existing clock mesh design process so there was no risk to the chip's development schedule. Full details at EE Times.
Cyclos (Berkeley, Calif.) said that the AMD (Sunnyvale, Calif.) has used the power-saving clock distribution technology in x86-compatible processor cores destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). Cyclos engaged with processor technology licensor ARM Holdings plc in the early years of its existence driving an expectation that an ARM processor core would be the first commercial demonstration of the technology.
However it is AMD's Piledriver 64-bit core, which operates at up to and in excess of 4-GHz clock frequency, that represents the first volume production-enabled implementation of resonant clock mesh technology, Cyclos said. Piledriver, fabricated in a 32-nm CMOS process, employs the resonant clocking to reduce clock distribution power by up to 24 percent, while maintaining previous clock-skew targets, Cylos said.