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Triple-level cell NAND flash memory explained

Posted on Friday, February 24 2012 @ 17:08:26 CET by


AnandTech dedicated an article to triple-bit-per-cell NAND flash memory, you can read it over here. This new technology increases the number of bits per cell to achieve higher capacities for the same amount of dollars, but there are also some weaknesses such as slower performance and worse endurance than MLC NAND.
Most of the time, SSD production costs are cut by shrinking the NAND die. Shrinking the die is the same as with CPUs: you move to a smaller manufacturing process, e.g. from 34nm to 25nm. In flash memory, this means you can increase the density per die and usually the physical die size is also smaller, meaning more dies from a single wafer. A die shrink is an effective way to lower costs but moving from one process to another takes time and the initial ramp of the new flash isn't necessarily cheaper. Once the new process has matured and supply has met demand, prices start to fall.

Since die shrinks are a relatively slow way to lower SSD prices and only contribute to steady reduction of prices, anyone looking to push higher capacity SSDs into the mainstream today will need something more. Right now, that "something more" is called Triple Level Cell flash, commonly abbreviated as TLC.




 



 

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