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Common Platform foundries to go FinFET with 14nm process

Posted on Friday, March 16 2012 @ 21:22:30 CET by

Bright Side of News reports the Common Platform, a collaboration of IBM, Samsung and GlobalFoundries, plans to adopt FinFET (aka 3D transistors) with their 14nm process around 2014-2015. This technology will be combined with chip stacking technology.
In a speech by Anna Hunter, Vice President of Foundry Business for Samsung, she expressed her gratitude to planar transistor "which took us through most of our professional lives and beyond" and announced that the members of the alliance will switch to FinFET transistor, which is also known as "3D transistor" in marketing naming convention of a semiconductor giant which shall remain unnamed here.

The alliance will offer FinFET to all of its customers at the 14nm process node, which paired with Fully Depleted Silicon-On-Insulator (FD-SOI) is pairing incredible transistor density with lower power consumption. The problem with the current partially-depleted SOI (PD-SOI) technology is that the pressure needed for SOI insulation to take place is decreasing yields due to pressure on the already strained silicon. When you pressure the strained silicon transistors, they tend to break. This is also the main reason why Common Platform Manufacturing Alliance, manufacturing arm of Common Platform Technology Alliance decided to go “SOI less” and go bulk with the 28nm and 20nm processes.
Full details over here.



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