Wafer maker Soitec announced a new fully depleted silicon wafer that makes it considerably easier and cheaper to produce chips with 3D transistors. Full details over here.
While Intel is on track to be the first to market with its Tri-Gate Transistor technology, fin-based Field Effect Transistors (FinFETs) have long been considered as the next big thing in semiconductor design. Unlike traditional planar transistors, FinFETs - a term coined by researchers from the University of California at Berkeley - are build on a silicon-on-insulator (SOI) substrate to create multigate transistors which extend into the third dimension.
A FinFET-based device promises a decrease in current leakage and a reduction in the short-channel effect as process sizes shrink to sub-20nm levels. The technology isn't without its issues, however: 3D transistors are significantly more complex to manufacture than planar transistors, with Intel thus far on track to be the first to push a related technology to market in a mass-produced semiconductor.
Soitec hopes to address the manufacturing issues that are preventing widespread use of FinFET designs with its new FD-3D wafer type. Constructed from a thin layer of silicon over a buried oxide layer, the silicon's thickness is customised according to the required fin height while the BOX layer provides isolation.